Display (DCN) IP Systems Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. The Role The AMD IP Systems Engineering Team is on the lookout for a dynamic, energetic IP Systems Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry leading technologies to market. The IP Systems Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development The Person Dynamic, self starter who has a passion for improving and innovating! As Systems Engineer, you will drive the planning, verification, and debug of various DCN hardware IP for forthcoming AMD APU SOC programs. Key Responsibilities Defining and executing the overall functional test plan and verification strategy for the AMD DCN IP Driving technical innovation to enhance AMD’s capabilities in DCN IP validation/verification, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. Debug of DCN IP issues found during pre-silicon, bringup, validation, and production phases of SOC programs Working closely with supporting teams in design, diagnostics, emulation, firmware, and driver to ensure readiness for first silicon arrival, enablement of DCN IP functionality, and debug of critical features. Engaging on pre-silicon verification efforts, including but not limited to FPGA-based emulation, Design Verification (DV), and other software/hardware modeling frameworks. Leading collaborative technical discussions to drive resolution on technical issues and roll out technical initiatives Developing knowledge of system architecture/debug and other IP’s Supporting issues on customer platforms as requested by customer support teams Preferred Experience Proven experience in digital logic/platform design, verification, or post-silicon verification. Strong programming/scripting skills (eg. C/C++, Perl, Ruby, Python) Experience with ASIC debug techniques and methodologies Experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc. Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization Knowledge of physical and protocol levels of common high speed interfaces an asset In-depth knowledge of PC architectures an asset Must have excellent written and verbal communication skills Must excel in a dynamic team working environment Leadership and mentoring skills a definite asset Must be a self starter and be able to independently drive tasks to completion Ability to be flexible in terms of responsibilities Academic Credentials Bachelor’s/Master’s degree in Computer Science or related field strongly preferred Location: Markham, Ontario Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

The role involves driving the planning, verification, and debug of DCN hardware IP for AMD APU SOC programs. Key duties include executing functional test plans and collaborating with cross-functional teams to ensure silicon readiness and functionality.

Candidates should have proven experience in digital logic or post-silicon verification and strong programming skills in languages like Python or C++. A Bachelor's or Master's degree in Computer Science or a related field is strongly preferred.

• RubySouhaitée
• PythonSouhaitée

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Digital Logic Design
• Post-Silicon Verification
• C/C++
• Perl
• Ruby
• Python
• ASIC Debug
• Protocol Analyzers
• Oscilloscopes
• Board-Level Debug
• High Speed Interfaces
• PC Architecture
• FPGA Emulation
• Design Verification
• Technical Leadership
• Functional Test Planning

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research

Formation minimale

Baccalauréat

Expérience minimale

5+ ans

Postuler avant le

13 sept. 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Niveau d’expérience

Mid-Senior level