SOC Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. The Role Join AMD's SOC design team and take technical ownership of the design and integration efforts that bring some of the industry's most advanced silicon to life. You'll work at the heart of the chip—integrating AMD and third-party IP, shaping SOC and IP feature enhancements, and driving decisions that influence top-level latency and performance. You'll guide a key area of the design while partnering closely with IP development, verification, front-end integration, and physical design teams. If you thrive on solving hard problems, seeing your work span from RTL to full-chip construction, and collaborating with talented engineers across the stack, this is where you'll do the best work of your career. The Person You're a self-driven engineer with the initiative to own problems from start to finish. You bring excellent written and verbal communication skills, along with strong analytical and problem-solving abilities that help you navigate complex, cross-functional challenges. Key Responsibilities Drive SOC-level design and integration Integrate IP, SOC-level fabric, voltage and clock crossings, clocks, resets, fuses, and I/O Develop RTL design and coding for various sections of the SOC and related logic Own SOC power design Perform static verification of the design (RTL, CDC, Power, Connectivity) Lead one of the domains listed above Preferred Experience Verilog RTL development with industry tools in a CPU, SOC, or ASIC environment SOC integration and architecture understanding System bus protocol knowledge (e.g., AXI, PCIe) Power implementation methodology and UPF Static timing analysis Collaboration with physical design teams and awareness of physical design requirements Formal verification techniques and tools Scripting skills (Ruby, Perl, Shell, TCL) a plus Academic Credentials BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE Background in SOC design and Verilog RTL development preferred Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Drive SOC-level design and integration by incorporating IP, fabric, and power design. Perform static verification and lead specific design domains to optimize top-level latency and performance.

Requires a degree in ECE/EEE with a strong background in Verilog RTL development and SOC architecture. Proficiency in system bus protocols, power implementation, and scripting languages is preferred.

• RubySouhaitée

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Verilog RTL Development
• SOC Integration
• AXI
• PCIe
• UPF
• Static Timing Analysis
• Formal Verification
• Ruby
• Perl
• Shell
• TCL
• CDC
• Power Design
• Physical Design
• ASIC Design
• System Bus Protocols

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research

Formation minimale

Baccalauréat

Expérience minimale

5+ ans

Postuler avant le

25 sept. 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Niveau d’expérience

Mid-Senior level