Sr. Manager, Physical Design Engineering, Annapurna Labs

Description Annapurna Labs, designs custom silicon powering AWS’s cloud infrastructure. Custom SoCs live at the heart of Amazon ML servers — including Inferentia and Trainium Systems — delivering high-performance ML inference and training at cloud scale. We’re looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs on latest tech nodes. This is a player-coach role: you will personally engage in the most critical technical decisions; chip-level floorplan architecture, multi-GHz timing convergence, high-speed I/O physical design, power delivery for KW class systems, and 2.5D / 3D integrations; while building a high-performing team and driving rigorous PPA targets, first-pass silicon success, and relentless continuous improvement. Key job responsibilities Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts. Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption. Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations. Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration. Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations. Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute. Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization. Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams. Basic Qualifications 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth. 10+ years hands-on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts. Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR-drop/EM signoff, physical verification, and tapeout. Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC). Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR-aware timing) and power integrity (static/dynamic IR-drop, EM, rush current, Ldi/dt, package-aware analysis). Proven expertise in high-speed PD (multi-GHz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low-power design (UPF, power gating, DVFS, retention). Experience with hierarchical methodologies for very large SoCs (>1B transistors). Expert scripting in TCL, Python, Perl. Preferred Qualifications Experience leading PD for AI/ML accelerators, GPUs, or high-performance data-center SoCs at leading semiconductor companies or hyperscalers. Direct 3nm GAA/Nanosheet experience; 2nm or sub-2nm engagement. Familiarity with CFET and backside power delivery (BSPDN). Quantifiable track record of continuous PPA improvement and metric-driven flow development across multiple projects and nodes. Strong program execution: managing concurrent tapeouts, milestone tracking, risk identification, and executive communication. Hands-on 2.5D/3D integration experience (CoWoS, EMIB, InFO, SoIC, Foveros) and chiplet strategy with UCIe. Track record deploying AI/ML-driven design methodologies in production flows. Experience with CPO, HBM4, silicon photonics, or CXL physical design. Multi-foundry technology assessment experience (TSMC, Samsung, Intel Foundry Services). Experience managing geographically distributed teams (U.S., Israel, global). Experience scaling PD organizations through 2x–3x growth. Patent portfolio or industry standards contributions (UCIe, IEEE). Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. As a total compensation company, Amazon's package may include other elements such as sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon offers comprehensive benefits including health insurance (medical, dental, vision, prescription, basic life & AD&D insurance), Registered Retirement Savings Plan (RRSP), Deferred Profit Sharing Plan (DPSP), paid time off, and other resources to improve health and well-being. We thank all applicants for their interest, however only those interviewed will be advised as to hiring status. CAN, ON, Toronto - 179,800.00 - 300,200.00 CAD annually Company - Amazon Development Centre Canada ULC Job ID: A10507605

Build and lead a world-class physical design team to deliver multi-billion-transistor ML accelerator SoCs on advanced technology nodes. Provide hands-on technical leadership for critical decisions including floorplan architecture, timing convergence, and 2.5D/3D integrations.

Requires 10+ years of hands-on ASIC/SoC physical design experience and 5+ years of people management leading teams of 8 or more engineers. Mastery of Synopsys and Cadence EDA ecosystems and deep expertise in advanced nodes (7nm, 5nm, 3nm) is essential.

• Health Insurance • Medical Insurance • Dental Insurance • Vision Insurance • Prescription Insurance • Basic Life Insurance • AD&D Insurance • Registered Retirement Savings Plan (RRSP) • Deferred Profit Sharing Plan (DPSP) • Paid Time Off • Sign-on Payments • Restricted Stock Units (RSUs)

• PythonSouhaitée

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Physical Design Engineering
• ASIC/SoC Design
• RTL-to-GDSII
• Timing Closure
• Floorplanning
• Power Delivery Network (PDN)
• Synopsys Fusion Compiler
• Cadence Innovus
• Siemens Calibre
• Static Timing Analysis (STA)
• 2.5D/3D Integration
• TCL
• Python
• Perl
• People Management
• PPA Optimization

• Engineering
• Technology
• Management & Leadership
• Software
• Manufacturing

Expérience minimale

10+ ans

Postuler avant le

19 sept. 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Niveau d’expérience

Mid-Senior level