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BTA Design ServicesSource d’offres vérifiée

Senior ASIC Design Engineer

Offre en anglais

Translate system-level requirements into detailed architecture and implement complex RTL logic for AI/HPC SOCs. Perform synthesis, timing closure, and lead lab bring-up and product integration.

  • Sur place
  • Ottawa, ON
  • Publié 16 juin 2026
  • Postuler avant le 14 sept. 2026
  • 1 poste

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Résumé du poste

About Us: Headquartered in Ottawa, BTA Design serves the electronic design community from Canada, specializing in ASIC and FPGA design and verification, and embedded software development services. We augment and enhance our clients’ teams and accelerate the development of complete designs. We’re adaptable and efficient, with a brilliant staff at our core. We aim to be the best at what we do. Our success continues to fuel growth. We are currently searching globally for a number of key technical resources, including a Senior ASIC Design Engineer with exceptional technical skills and significant experience. This is an outstanding opportunity to work on AI/HPC SOCs in the custom silicon business unit of a large well-known Tier 1 fabless semiconductor company. Key Responsibilities: Translate system-level requirements into clear, detailed, implementable architecture and design specifications. Develop synthesis and timing constraints for complex block and sub-systems. Design and implement complex RTL logic (mainly Verilog or System Verilog), run block-level simulation, ASIC synthesis, timing closure. Interface with the verification team, design team, hardware team and support team. Perform lab bring-up, product integration and support. Provide technical support to customers and lead them through complex technical issues. Key Qualifications: A minimum of 5 years of relevant experience in ASIC design. Experience with modern day ASIC development including complex RTL logic design, synthesis, STA, lint, LEC, and understanding of PnR. Experience developing synthesis and timing constraints for complex logic blocks and sub-systems on large, timing critical digital designs. Experience in a lab environment, troubleshooting issues up to the system level. Experience or knowledge in one or more of the following: ARM A** or RISC-V Application Processor Sub-Systems, Processor Fabric Interfaces (ARM preferred, coherent and non-coherent), Caches, Non-Volatile memory, DSP Cores, AI Acceleration Cores, Networking Switch/Router Datapaths, Packet Processing, OTN, Ethernet. Experience with one or more industry standard interfaces e.g. 10/25/40/100Gb Ethernet and OTN, PCIe, SPI, I2C, USB, AXI, AHB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, NV Memories Test verification and scripting experience is a must. Track record as a self-starter, a team player and a leader. Compensation: $140,000 to $190,000 plus company bonus and benefits plan. Salary is heavily dependent on individual experience and capability. This is a new position. Only candidates selected for an interview will be contacted. Artificial Intelligence tools are not used in the evaluation and selection of candidates. Why Work Here? We offer interesting work in challenging, stimulating technical environments with companies that lead the world in technology and innovation. We recognize that our strength is in the individuals who join our team, so at BTA Design Services, we foster an environment where everyone is appreciated, trusted and engaged. We recognize that work-life balance is important and we strive to provide our employees with challenging roles that also allow them to enjoy family, friends and life outside of work.

Ce que vous ferez

Translate system-level requirements into detailed architecture and implement complex RTL logic for AI/HPC SOCs. Perform synthesis, timing closure, and lead lab bring-up and product integration.

Exigences

Requires at least 5 years of ASIC design experience with proficiency in RTL, synthesis, and timing constraints. Knowledge of processor sub-systems, industry-standard interfaces, and scripting is essential.

Avantages

• Company Bonus • Benefits Plan

Autres compétences pertinentes

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

  • ASIC Design
  • RTL Logic
  • Verilog
  • System Verilog
  • Synthesis
  • Static Timing Analysis
  • Lint
  • LEC
  • PnR
  • ARM Architecture
  • RISC-V
  • PCIe
  • AXI
  • AMBA
  • DDR
  • Scripting

Domaines d’emploi

  • Engineering
  • Technology
  • Software
  • Manufacturing
  • Science & Research

Renseignements supplémentaires

Expérience minimale
5+ ans
Postuler avant le
14 sept. 2026
Langue de l’offre
anglais
Heures de travail
40 heures par semaine