Senior FPGA Design Engineer

About Us: Headquartered in Ottawa, BTA Design serves the electronic design community in Canada and beyond, specializing in ASIC and FPGA design and verification, and embedded software development services. We augment and enhance our clients’ teams and accelerate the development of complete designs. We’re adaptable and efficient, with a brilliant staff at our core. We aim to be the best at what we do. Our success continues to fuel growth. We are currently searching globally for a number of key technical resources, including a Senior FPGA Design Engineer. Key Responsibilities The ASIC/FPGA Designer will work in an exciting team environment and will have the following responsibilities: Understand high-level requirements and translate them into detailed specifications. Design and implement RTL logic (mainly Verilog or System Verilog), run block-level simulation, FPGA synthesis, backend and timing closure. Interface with the verification team, design team, hardware team and support team. Perform lab bring-up, product integration and support. Provide technical support to customers and lead them through complex technical issues. Key Qualifications A minimum of 5 years of relevant experience in the FPGA design field. Experience with high-speed FPGA Design Flow using Verilog and SystemVerilog. Experience with Xilinx Vivado and recent Xilinx FPGA device families in complex high-speed designs or experience with Intel Quartus and the Intel Agilex device family in complex high-speed designs. Experience with complex asynchronous clock boundaries & high-speed serial interfaces. Experience in a lab environment, troubleshooting issues up to the system level. Experience with industry standard interfaces e.g. Ethernet, SONET, PCIe, SPI, I2C, USB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, 4G, LTE, 5G, O-RAN, 3GPP. Test verification and scripting experience is a plus. Track record as a self-starter, a team player and a leader. Strong scripting skills. Excellent ability to work in a team. Software background would be an asset. Compensation: $120,000 to $170,000 plus company bonus and benefits plan. Salary is heavily dependent on individual experience and capability. This is a new position. Only candidates selected for an interview will be contacted. Artificial Intelligence tools are not used in the evaluation and selection of candidates.

The engineer will translate high-level requirements into detailed specifications and implement RTL logic using Verilog or SystemVerilog. Responsibilities include performing FPGA synthesis, timing closure, lab bring-up, and providing technical support to customers.

Candidates need at least 5 years of FPGA design experience with proficiency in Xilinx Vivado or Intel Quartus. Expertise in high-speed serial interfaces and industry-standard protocols like PCIe and Ethernet is required.

• Company Bonus • Benefits Plan

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• FPGA Design
• Verilog
• SystemVerilog
• Xilinx Vivado
• Intel Quartus
• RTL Logic
• Timing Closure
• High-speed Serial Interfaces
• Lab Bring-up
• Scripting
• Ethernet
• PCIe
• AMBA
• DDR/SDRAM/DMA
• 5G
• O-RAN

• Engineering
• Technology
• Software

Expérience minimale

5+ ans

Postuler avant le

14 sept. 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine