Cadence is a leader in electronics and system design, offering innovative software, hardware, and IP solutions for diverse industries, including automotive, aerospace, and healthcare.
San Jose, California
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Sur place · Burnaby
Build scalable data processing infrastructure and ingestion pipelines for massive circuit designs using a Python-based platform. Implement task distribution, fault-tolerant scheduling, and high-performance I/O for distributed solver results.
Sur place · Burnaby
Build scalable data processing infrastructure and ingestion pipelines for massive circuit designs using a Python-based platform and C++ solvers. Implement task distribution, fault-tolerant scheduling, and resource management across compute clusters.
Sur place · Burnaby
The engineer will contribute to the core distributed infrastructure for a Python-based platform, focusing on building data ingestion pipelines for large-scale netlists and developing fault-tolerant scheduling for task distribution across compute clusters. Responsibilities also include implementing high-performance I/O for multi-terabyte circuit databases and developing scalable visualization techniques for simulation results.
Sur place · Burnaby
The engineer will contribute to the core distributed infrastructure for a Python-based platform, focusing on building data ingestion pipelines for large-scale netlists and implementing high-performance I/O for multi-terabyte circuit databases. Responsibilities also include implementing fault-tolerant scheduling for task distribution across compute clusters and developing scalable visualization for simulation results.
Sur place · Burnaby
The Circuit Analysis Engineer will design, implement, and maintain software for transistor-level electrical circuit simulation. They will also contribute to modernizing VLSI circuit simulation tools and collaborate with cross-functional teams.
Sur place · Burnaby
The Circuit Analysis Engineer will design, implement, and maintain software for transistor-level electrical circuit simulation. They will also contribute to modernizing VLSI circuit simulation tools to integrate with emerging Agentic AI frameworks.
Sur place · Burlington
Provide technical and sales support for Virtual Manufacturing & Costing simulation software, specifically Simufact and FTI. Create training materials, tutorials, and documentation while collaborating with product development to drive software quality.
Sur place · Toronto
Develop and enhance functional verification environments to add new features and ensure clean customer configurations. Responsible for maintaining design quality metrics and supporting customers with verification environment issues.
Télétravail · New York, New York, United States
Drive revenue growth and manage complex strategic opportunities for Systems Products, including PCB design and CAE workflows. Partner with cross-functional teams to maximize pipeline generation and execute account penetration strategies.
Sur place · Montréal
The engineer will develop and verify analog and mixed-signal behavioral models using SystemVerilog to ensure design intent is met. They will also collaborate with cross-functional teams to debug failures and maintain verification infrastructure for complex silicon designs.
Sur place · Canada
Build and align strategic co-selling and communication collaborations between Cadence and Tier 1 ecosystem partners to increase market share. Drive focused strategies and programs that deliver measurable business development, relationship, and public relations results.
Sur place · Toronto
Provide tools and technical support to circuit implementation teams designing analog IP for various industries using Cadence software and AI. Collaborate with engineering teams to improve design flows, methodologies, and EDA tool infrastructure.
Sur place · Montréal
The engineer will develop firmware for high-speed SERDES PHY, covering architecture, implementation, and verification. Responsibilities include debugging firmware issues in simulations and post-silicon validation to ensure optimal performance and robustness.
Sur place
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role is for an existing vacancy. Présentation de l’entreprise L’avenir des solutions d’IP est arrivé L’innovation électronique est présente partout, des capteurs intelligents aux villes intelligentes, et transforme la façon dont les gens travaillent, vivent et se divertissent. Cadence est fière de contribuer à cette innovation, non seulement à titre de chef de file mondial en automatisation de la conception électronique (EDA) depuis plus de 25 ans, mais aussi comme chef de file d…
Sur place · Toronto
The role involves providing high-level technical leadership and architectural decisions to drive the success of future Cadence products. The architect will lead cross-functional initiatives, mentor junior staff, and serve as a technical consultant to executive management.
Sur place · Montréal
Responsible for the verification of digital RTL and the development of reusable verification components and environments. This includes flow development, test plan execution, and achieving functional and code coverage closure.
Sur place · Toronto
The role involves participating in or leading next-generation physical design, methodology, and flow development, particularly for advanced technology nodes. Key tasks include performing physical design implementation steps such as floor planning, power grid design, place and route, and ensuring signoff for timing, power/signal integrity, and physical verification.
Sur place · Ottawa
The candidate will be responsible for the verification of digital RTL and the development of reusable verification components and environments. They will also contribute to all aspects of digital verification including flow development, test plan development, and execution.
Sur place · Ottawa
Responsible for the verification of digital RTL and the development of reusable verification components and environments. This includes flow development, test plan execution, and achieving functional and code coverage closure.
Sur place · Toronto
The Senior Program Manager will coordinate R&D development projects and key customer engagements within the Design IP Group. They are responsible for defining project scope, monitoring progress, and collaborating across departments to ensure effective execution.