Memory Layout Design Engineer

Position: Memory Layout Design Engineer Location: Vancouver, BC (On-site) Employment Type: Full-Time Total Experience: 5 + years Job Summary: We are looking for an experienced Technology Lead – Memory Layout to design and develop high-performance custom memory layouts for advanced semiconductor technologies. The ideal candidate should have strong expertise in memory layout design, physical verification, FinFET technologies, and memory architectures. Key Responsibilities: · Design and develop custom memory layouts and memory leaf cell libraries from scratch. · Optimize layouts for performance, power, and area (PPA). · Work on various memory architectures and top-level layout integration. · Perform physical verification (DRC, LVS, ERC) and resolve layout issues. · Develop layouts using Cadence Virtuoso and verify designs with Calibre. · Collaborate with cross-functional teams to ensure high-quality and timely project delivery. Required Qualifications: · Bachelor's degree in engineering or equivalent experience. · 5+ years of experience in compiler/custom memory layout design. · Hands-on experience with memory leaf cell layout development. · Strong knowledge of memory architectures and FinFET technology (3nm/5nm). · Experience with DRC, LVS, ERC, boundary conditions, Cadence Virtuoso, and Calibre. · Strong problem-solving, communication, and teamwork skills. · Must be willing to work on-site in Vancouver, BC or relocate.

The role involves designing and developing high-performance custom memory layouts and leaf cell libraries from scratch. It also requires optimizing layouts for power, performance, and area while performing rigorous physical verification.

Candidates must have a bachelor's degree and over 5 years of experience in custom memory layout design, specifically with FinFET technologies (3nm/5nm). Proficiency in Cadence Virtuoso and Calibre for DRC, LVS, and ERC is essential.

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Memory Layout Design
• Physical Verification
• FinFET Technology
• Memory Architectures
• Cadence Virtuoso
• Calibre
• DRC
• LVS
• ERC
• PPA Optimization
• Custom Memory Layouts
• Leaf Cell Library Development

• Engineering
• Manufacturing
• Technology
• Science & Research

Formation minimale

Baccalauréat

Expérience minimale

5+ ans

Postuler avant le

22 août 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Niveau d’expérience

Mid-Senior level

Mode de candidature

La candidature directe est offerte