Design Verification Engineer

ASIC Programs (Switch/NIC) DV • Lead or contribute to verification of 4–5 ASIC design blocks. • Develop UVM-based verification environments, sequences, tests, debug, and coverage closure. • Strong experience in SystemVerilog/UVM. • Experience with PCIe, UCIe 2.0, and Ethernet protocols. • Ability to independently own verification deliverables. • Support customer collaboration in EST timezone. Required Skills • Strong SystemVerilog/UVM verification experience • Knowledge and/or hands-on experience with: o UCIe 2.0 o PCIe o Ethernet • Ability to own design blocks independently and drive verification closure Responsibilities The DV team is expected to: • Own verification of 4–5 design blocks per ASIC • Develop and execute sequences • Perform test development and debug • Drive coverage collection and closure • Own end-to-end verification execution for assigned blocks • The customer will own the testbench infrastructure.

The engineer will lead the verification of multiple ASIC design blocks by developing UVM-based environments and executing sequences. They are responsible for driving coverage collection, debugging, and ensuring end-to-end verification closure for assigned blocks.

Candidates must have strong experience in SystemVerilog and UVM for design verification. Proficiency with PCIe, UCIe 2.0, and Ethernet protocols is required to independently own and drive verification deliverables.

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Systemverilog
• Uvm
• Asic Verification
• Pcie
• Ucie 2.0
• Ethernet
• Test Development
• Debug
• Coverage Closure
• Sequence Development
• Design Verification

Expérience minimale

5+ ans