ASIC Verification Engineer (33722)
Offre en anglaisLead the development of verification infrastructure and create System Verilog/UVM-based protocol and traffic generators. Develop and execute comprehensive test plans and self-checking tests for complex digital ASICs.
- Sur place
- Ottawa, ON
- Publié 6 août 2026
- Postuler avant le 5 sept. 2026
- 1 poste
Résumé du poste
Our client is seeking a highly experienced ASIC Verification Engineer to help develop and verify complex digital ASICs in a collaborative, geographically diverse environment. Key Responsibilities Lead the development of verification infrastructure for advanced ASIC designs Create System Verilog/UVM-based protocol and traffic generators/checkers Develop and execute test plans based on functional and standards requirements Define, develop, and run self-checking tests for complex digital ASICs Required Qualifications Bachelor’s degree in computer science or electrical engineering (master’s preferred) 8+ years of experience in ASIC verification Proven experience in developing and implementing test plans at block or sub-chip levels Proficiency in System Verilog and scripting languages such as Python Deep understanding of UVM methodology Experience with assertions, functional coverage, code coverage, and formal verification tools Strong communication skills and ability to work effectively in a distributed team Preferred Skills Knowledge of DSP and/or FEC technologies ,
Ce que vous ferez
Lead the development of verification infrastructure and create System Verilog/UVM-based protocol and traffic generators. Develop and execute comprehensive test plans and self-checking tests for complex digital ASICs.
Exigences
Requires a bachelor's degree in computer science or electrical engineering and over 8 years of experience in ASIC verification. Proficiency in System Verilog, Python, and UVM methodology is essential.
Compétences indiquées
- PythonSouhaitée
Autres compétences pertinentes
Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.
- ASIC Verification
- System Verilog
- UVM
- Python
- Test Planning
- Assertions
- Functional Coverage
- Code Coverage
- Formal Verification
- DSP
- FEC Technologies
Domaines d’emploi
- Engineering
- Technology
- Software
Renseignements supplémentaires
- Formation minimale
- Baccalauréat
- Expérience minimale
- 10+ ans
- Postuler avant le
- 5 sept. 2026
- Langue de l’offre
- anglais
- Heures de travail
- 40 heures par semaine
- Niveau d’expérience
- Mid-Senior level