Design Verification Engineer

Résumé du poste

The role involves defining and executing comprehensive verification strategies for complex Display IP and SoC designs. Key tasks include developing UVM testbenches, creating functional coverage plans, and applying formal verification methodologies to ensure first-pass silicon success.

Détails du poste

Title: Verification Engineer V Location: Markham, ON (Hybrid - 3 days per week onsite ) Duration: 8 Months (Possible extension) Pay Range: $92 to $102 per hour on T4 The Role Join Display IP team that is building industry-leading semiconductor products and technologies. As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs. You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market. The ideal candidate is passionate about verification methodologies, possesses strong expertise in SystemVerilog/UVM-based verification environments, and has hands-on experience with formal verification, functional coverage planning, and coverage-driven verification. This individual will thrive in a collaborative environment and enjoy solving complex technical challenges across all phases of product development. Key Responsibilities • Define and execute comprehensive verification strategies for complex IP and subsystem designs. • Develop verification plans based on architecture and design specifications. • Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components. • Create directed and constrained-random test scenarios to validate functionality, performance, and robustness. • Develop functional coverage plans and coverage models, and drive coverage closure. • Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics. • Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis. • Develop and maintain assertion-based verification (SVA) infrastructure and verification content. • Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues. • Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle. • Analyze verification metrics and recommend improvements to verification quality and efficiency. • Contribute to verification methodology development, automation, and continuous process improvement. Preferred Experience • 8-10+ years of experience in ASIC, IP, or SoC verification. • Strong expertise in SystemVerilog, UVM, and constrained-random verification methodologies. • Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure. • Hands-on experience with formal verification methodologies and industry-standard formal verification tools. • Strong understanding of assertion-based verification (SVA) and formal property development. • Experience creating reusable verification environments, verification IP, and verification infrastructure. • Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies. • Experience with simulation, regression management, coverage analysis, and debug tools. • Experience working through multiple successful silicon product cycles. • Strong communication and collaboration skills. Preferred Technical Skills Experience in one or more of the following areas is considered an asset: • Display IP and display subsystem verification • Formal verification and assertion-based verification (ABV) • Functional coverage architecture and coverage closure methodologies • Graphics, multimedia, and video processing pipelines • Display interfaces and protocols including DisplayPort, eDP, HDMI, and MIPI • High-speed interfaces and protocols • Memory subsystem verification

Ce que vous ferez

The role involves defining and executing comprehensive verification strategies for complex Display IP and SoC designs. Key tasks include developing UVM testbenches, creating functional coverage plans, and applying formal verification methodologies to ensure first-pass silicon success.

Exigences

Candidates should have 8-10+ years of experience in ASIC or SoC verification with strong expertise in SystemVerilog and UVM. Proficiency in formal verification, assertion-based verification (SVA), and experience with display protocols is highly preferred.

Compétences indiquées

• Root Cause Analysis · Souhaitée

Autres compétences pertinentes

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• SystemVerilog
• UVM
• Formal Verification
• Functional Coverage
• SVA
• ASIC Verification
• SoC Verification
• Constrained-Random Verification
• DisplayPort
• HDMI
• MIPI
• eDP
• Digital Design
• Computer Architecture
• Regression Management
• Root-Cause Analysis

Domaines d’emploi

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research