Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels)

Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Do you ever wonder when connected devices become thinking devices? Be part of the group that is working on technology that will bring “Cognition” to all connected devices: That means devices that don’t just react to their surroundings, they interact with the world. We are a compact, tightly knit ASIC IP team of architects, design, and verification engineers. We create HW IP in the heart of the Snapdragon DSP Neural Processing Unit (NPU) that works in coordination with the other NPU components to accelerate AI machine learning, video and other dsp applications. We’re continuously evolving and improving our design and verification architectures to tackle complex engineering problems. To achieve the high standards of Qualcomm products, our team members contribute with a variety of skills and participate in many aspects of the design, verification, and final product evaluation processes. We are looking for few good ASIC Design Verification Engineers to be part of our team to innovate and design leading edge Qualcomm Snapdragon DSP processors that will empower AI and video processing applications and products. We are open to all levels of applicants; the role (Jr, Sr., Staff) and responsibility will be commensurate with experience. New Position As part of our team your responsibilities would include: Verification of a complex IP block using UVM methodology Resolving architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision Collaborating closely with the Design team to test, debug and close coverage on the design Modifying testbench components such as scoreboard, agents, sequences, to verify new features Writing tests in SystemVerilog Writing functional coverage and assertions using SystemVerilog Regression maintenance and triaging of test failures Contributing to testbench architecture and optimization Contributing to testplan implementation and verification methodology Supporting integration testing of the design Performance testing Qualifications Strong problem solving and analytical thinking skills Excellent communication skills Self-motivated, goal oriented, team player New Grad Bachelors - Engineering, Computer Engineering Understanding of digital logic Understanding of objected oriented programming concepts some design or DV experience, whether in work, co-op, or coursework Senior or above: 2+ years of direct experience in ASIC verification Experience with verification methodology (UVM, assertions, coverage-driven constrained-random verification) Experience with scripting languages (Python, CShell) Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. Pay range and Other Compensation & Benefits: $124,200.00 - $174,200.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer. If you would like more information about this role, please contact Qualcomm Careers.

The engineer will verify complex IP blocks using UVM methodology and collaborate with the design team to close coverage and resolve technical issues. Responsibilities also include modifying testbench components, writing tests in SystemVerilog, and supporting integration and performance testing.

Candidates must hold at least a Bachelor's degree in Engineering or a related field with relevant experience in ASIC design or verification. Senior-level applicants require at least 2 years of direct experience in ASIC verification and proficiency in UVM and scripting languages.

• Annual discretionary bonus program • Annual RSU grants • Competitive benefits package

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• ASIC design
• Verification
• UVM
• SystemVerilog
• Digital logic
• Object-oriented programming
• Python
• CShell
• Functional coverage
• Assertions
• Testbench architecture
• Performance testing
• Debugging
• Problem solving
• Analytical thinking
• Design Verification
• Analytical Thinking
• REST Assured
• Self-Motivation
• Architectural Design
• Digital Logic
• Communication
• Integration Testing
• Computer Engineering
• Connected Devices
• Digital Signal Processing
• Sales
• Problem Solving
• Python (Programming Language)
• Machine Learning
• Programming Concepts
• SystemVerilog (Direct Programming Interface)
• Scripting
• Coordinating
• Performance Testing
• Application Specific Integrated Circuits
• Video Processing
• React.js (Javascript Library)
• Goal-Oriented

• Engineering
• Technology
• Software
• ASIC Design Verification Engineer
• Verification Engineer
• Industrial and Production Engineers
• Electrical Engineers

Formation minimale

Baccalauréat

Expérience minimale

2+ ans

Langue de l’offre

anglais

Heures de travail

40 heures par semaine