SMTS Logic Design

Résumé du poste

The candidate will contribute to the full product lifecycle of PCIe Gen6/Gen7 switch IP, including architecture definition, RTL implementation, and design closure. They will also mentor junior engineers and collaborate with verification teams to ensure high-performance silicon delivery.

Détails du poste

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of Technical Staff (SMTS) – Logic Design Engineer to join our PCIe Switch Architecture and Design team in Montreal, Canada. In this role, you will be working with some of the brightest inventors and engineers in the world developing next-generation PCIe Gen6/Gen7 switch products that make data faster and safer. As a Senior Member of Technical Staff (SMTS) – Logic Design Engineer, you’ll play a pivotal role in PCIe Gen6/Gen7 switch IP development, contributing to architecture definition, micro-architecture development, RTL implementation, and design closure of high-performance ASIC IP. In this full-time role, you’ll report directly to the Logic Design leadership team. Our PCIe Switch Architecture and Design team is dedicated to developing scalable, high-performance switch IP for advanced connectivity solutions, and your contributions will be instrumental in delivering next-generation PCIe switch product milestones. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities The successful candidate will contribute across the full product lifecycle, from architecture and micro-architecture through RTL implementation, verification support, emulation, and design closure. Analyze product requirements and contribute to architecture and micro-architecture development for next-generation PCIe Gen6/Gen7 switch products. Define and document complex hardware subsystems, including PCIe switch fabric, port controllers, routing and arbitration logic, flow control and credit management, buffer management, power management features, and configuration/register infrastructure. Review specifications and identify implementation risks, performance bottlenecks, scalability concerns, and opportunities for design optimization. Develop high-quality, synthesizable RTL using SystemVerilog and design high-performance pipelines capable of supporting PCIe Gen6 and Gen7 data rates. Implement timing-conscious and physically-aware architectures suitable for advanced process nodes, ensuring RTL is scalable, reusable, and maintainable. Lead the development of significant design blocks independently and drive resolution of complex technical issues spanning architecture, implementation, and verification. Mentor junior and intermediate engineers, participate in design reviews, and provide technical guidance across the team. Collaborate with verification engineers to define verification strategies, coverage goals, and debug approaches. Support block, subsystem, emulation, FPGA, and silicon debug activities, including analysis of protocol, performance, and functional issues discovered during verification or customer engagements. Conduct RTL reviews, enforce coding guidelines, and support CDC, RDC, lint, synthesis, and timing closure activities. Participate in continuous improvement of design methodologies, automation flows, and development processes. Qualifications Candidates should demonstrate strong ASIC/SoC logic design experience, technical leadership, and the ability to deliver complex silicon IP from architecture through tape-out. BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related discipline. 8+ years of ASIC/SoC logic design experience with proven delivery of complex silicon products from architecture through tape-out. Expert knowledge of SystemVerilog, RTL design methodologies, and ASIC development flows. Strong understanding of pipelined architectures, resource arbitration, state machine design, clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power design techniques. Experience with synthesis and timing closure, including industry-standard EDA tools such as Synopsys Design Compiler/Fusion Compiler, Cadence Genus, SpyGlass, and Questa/Visualizer. Preferred: deep knowledge of PCIe Gen5/Gen6/Gen7 protocol architecture and experience designing PCIe switches, root complexes, PCIe endpoints, or high-speed interconnect fabrics. Preferred: familiarity with CXL, PTM, ATS/PASID/PRI, SR-IOV, and PCIe power management features. Preferred: experience with emulation platforms such as HAPS, Palladium, or Veloce, and experience with performance modeling or architectural simulation in Python or C++. Strong problem-solving, analytical, communication, documentation, mentoring, and technical leadership skills, with the ability to work effectively across architecture, verification, software, and customer-facing teams. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-HYBRID #LI-RF1

Ce que vous ferez

The candidate will contribute to the full product lifecycle of PCIe Gen6/Gen7 switch IP, including architecture definition, RTL implementation, and design closure. They will also mentor junior engineers and collaborate with verification teams to ensure high-performance silicon delivery.

Exigences

Candidates must have 8+ years of ASIC/SoC logic design experience and a degree in Electrical or Computer Engineering. Expert knowledge of SystemVerilog, RTL methodologies, and industry-standard EDA tools is required for this role.

Avantages

• Competitive compensation package • Bonus • Equity • Employee benefits

Compétences indiquées

• Analytical · Souhaitée
• Recruitment · Souhaitée
• Technical · Souhaitée
• analysis · Souhaitée
• Leadership · Souhaitée
• staff · Souhaitée
• Teams · Souhaitée
• management · Souhaitée
• Communication · Souhaitée
• Development · Souhaitée
• Customer · Souhaitée
• Configuration · Souhaitée

Autres compétences pertinentes

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Logic Design
• PCIe Gen6/Gen7
• SystemVerilog
• RTL Implementation
• ASIC/SoC Design
• Timing Closure
• Synthesis
• Pipelined Architectures
• Clock-domain crossing
• Reset-domain crossing
• Low-power design
• Technical leadership
• Verification support
• Emulation
• Silicon debug
• Semiconductors
• Low Power Design
• Questa Advanced Verification (Siemens EDA)
• Veloce (Siemens EDA)
• Pipelines
• Technical Issues
• Product Requirements
• Technical Leadership
• Artificial Intelligence
• Electrical Engineering
• Arbitration
• Automation
• Management
• C++ (Programming Language)
• Clock Domain Crossing
• Textiles
• Communication
• Computer Engineering
• Continuous Improvement Process
• Credit Management
• Debugging
• Logic Synthesis
• Electronic Design Automation
• Flow Control
• Field-Programmable Gate Array (FPGA)
• Leadership
• Scalability
• Innovation
• Problem Solving
• Python (Programming Language)
• Product Lifecycle Management
• Machinery Design
• Mentorship
• Milestones (Project Management)
• Nodes (Networking)

Domaines d’emploi

• Technology
• Engineering
• Software
• Logic Design Engineer
• Manufacturing Process Engineer
• Industrial and Production Engineers
• Manufacturing Engineers
• Industrial Engineers