ASIC Digital Verification Engineer

About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com [https://www.globenewswire.com/Tracker?data=eh05Boj9A3xOr6pxGz6VKvfwD3vaBj8ZQFOZ8KMHvM5cCnzTHKTWtWW-q-KBuKoH7G4-VSVFiVQ6RuiKbXWXfw&utm_source=sitime.com&utm_medium=site]. Job Summary Our Ottawa office is looking for a talented Digital Verification Engineer to join our team. Our team is developing industry-leading mixed-signal Digital PLL Application specific integrated circuits. You can be a part of a growing mixed design and verification team giving you a chance to make a significant impact. You would not only be contributing to the actual testcase development but also be part of the verification planning and the continuous improvement of our verification environment using the latest methodologies. Responsibilities: * Define and implement self-checking test cases based on functional requirements * Contribute to our ever-evolving verification infrastructure components * Triage of regressions, debug of RTL and Gate level simulations, analysis of coverage, and working with other teams to resolve issues and achieve verification closure * Work with diverse design and verification team members, local and remote Qualifications & Requirements (Education must be included): * Understanding standard specifications/ functional specifications/ feature enhancements for the product to create and execute detailed verification plans * Knowledge of SystemVerilog and UVM environments for digital verification * Experience with Synopsys and/or Cadence simulation tools * Experience with System Verilog assertions, functional coverage, and code coverage * Ability to work in a Unix/Linux operating system environment It is not necessary to meet all job requirements to be a qualified candidate for the position. Desired Characteristics & Attributes: * Fast learner with the ability to work under minimal supervision * Effective team player with good communication skills Compensation Range: At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. The annual base salary range for this role is CAD 75,770 - CAD104,190. The final offer is determined by factors such as location, experience, education, and training. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success. SiTime is an Equal Opportunity Employer [http://www.sitime.com/images/EEO-is-the-law.pdf]. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify [http://www.sitime.com/images/E-Verify-Participation-Poster.pdf] program. Learn More about SiTime: Review the Get to Know SiTime [https://www.sitime.com/company/careers] section of our career page to explore our culture, values, and what makes us unique. * Innovation on Top – Philosophies of Innovation with Rajesh Vashist [https://www.innovatorsontap.com/podcast/the-philosophy-of-innovation-w-rajesh-vashist] * Fabrication Knowledge – An Interview with Rajesh Vashist [https://www.fabricatedknowledge.com/p/an-interview-with-rajesh-vashist-3e0#details] * SiTime Corporation – YouTube [https://www.youtube.com/user/sitimecorp/videos] #li-sitime

The engineer will define and implement self-checking test cases while contributing to the evolution of verification infrastructure. They will also perform regression triage, debug RTL and gate-level simulations, and collaborate with teams to achieve verification closure.

Candidates must have knowledge of SystemVerilog and UVM environments for digital verification. Experience with Synopsys or Cadence simulation tools and working in a Unix/Linux environment is required.

• Quarterly bonus • Equity grants

• LinuxSouhaitée

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• SystemVerilog
• UVM
• Digital verification
• RTL
• Gate level simulation
• Functional coverage
• Code coverage
• SystemVerilog assertions
• Synopsys
• Cadence
• Unix
• Linux
• Mixed-signal design
• Verification planning
• Testcase development
• Semiconductors
• Talent Acquisition
• Resilience
• Planning
• Quick Learning
• Automation
• Code Coverage
• Communication
• Continuous Improvement Process
• Debugging
• Functional Specification
• Functional Requirement
• Scalability
• Integrated Circuits
• Innovation
• Simulations
• SystemVerilog (Direct Programming Interface)
• Test Case
• Triage
• Reliability
• Internet Of Things (IoT)
• Wearables

• Technology
• Engineering
• Software
• Digital Verification Engineer
• Verification Engineer
• Industrial and Production Engineers
• Electrical Engineers

Expérience minimale

2+ ans

Langue de l’offre

anglais

Heures de travail

40 heures par semaine