Sr. Engineer, SoC Design Verification Engineer, System Management Controller

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. You’ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems. This role is hybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills. Experienced in writing test plans, building infrastructure, and debugging hardware/software flows. Comfortable working with remote mentorship and distributed teams. Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification. What We Need Develop and maintain SMC tests and supporting DV infrastructure. Write, execute, and track test plans for chiplet and multi-chip SoC designs. Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT. Triage, analyze, and debug issues in close collaboration with design and architecture teams. What You Will Learn Build deep expertise in system management and multi-die SoC verification. Gain hands-on exposure to advanced interconnect standards like UCIe and BoW. Explore co-simulation methodologies including Cocotb. Learn how AI tools can accelerate test generation, infrastructure, and debug workflows. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Develop and maintain tests and DV infrastructure for the System Management Controller to enable seamless multi-chip integration. Triage and debug hardware/software issues in collaboration with design and architecture teams.

Proficiency in SystemVerilog, SV-UVM, Python, and C/C++ is required for building verification infrastructure and executing test plans. Candidates should be comfortable with remote mentorship and the use of AI-assisted tools to accelerate workflows.

• PythonSouhaitée

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• SystemVerilog
• SV-UVM
• Python
• C/C++
• SoC Design Verification
• Test Planning
• Hardware Debugging
• Infrastructure Building
• Multi-chip Integration
• System Management Controller
• UCIe
• BoW
• Cocotb
• AI-assisted Tools

• Engineering
• Technology
• Software
• Manufacturing

Expérience minimale

5+ ans

Postuler avant le

25 sept. 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Exigences de lieu

Country, Greater Toronto Area, Canada

Niveau d’expérience

Mid-Senior level