Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets

Résumé du poste

Establish and execute verification strategies across blocks, subsystems, and chip-level functions for advanced I/O and chipset solutions. Develop verification plans and maintain reusable SystemVerilog/UVM environments to ensure verification closure and successful tape-out.

Détails du poste

Senior ASIC Verification Engineer – SystemVerilog / UVM / High-Speed I/O / SoC / Chipsets We are currently partnered with a semiconductor technology organisation developing advanced I/O and chipset solutions that connect die-to-die interfaces with high-speed, multi-protocol I/O. The technology combines advanced interconnect standards, high-speed networking, switching, and embedded management capabilities. As part of their continued development of complex silicon solutions, they are looking to hire a Senior ASIC Verification Engineer to establish and execute verification strategies across blocks, subsystems, and chip-level functions. The role involves close collaboration with architecture, RTL, verification, firmware, physical design, and IP teams, with ownership extending through verification closure and tape-out. Key responsibilities Develop verification plans that map requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria Translate architectural and design requirements into measurable verification objectives Design and maintain reusable SystemVerilog/UVM verification environments, including sequences, agents, scoreboards, reference models, and assertions Integrate third-party verification IP (VIP) and models Verify configured IP and end-to-end connectivity across protocol and PHY interfaces Verify static switching configurations, protocol modes, data integrity, latency, throughput, reset behaviour, and recovery mechanisms Key requirements 10+ years of hands-on ASIC design verification experience Proven ownership of verification activities through tape-out and formal sign-off Expert-level SystemVerilog and UVM experience Strong understanding of constrained-random verification and reusable testbench architecture Proven experience developing verification plans, defining coverage objectives, debugging complex failures, and driving verification closure Experience verifying high-speed interfaces, complex SoCs, networking ASICs, or die-to-die interconnect technologies Hands-on experience integrating verification IP and developing reference models and scoreboards Keywords Senior ASIC Verification Engineer / Senior Verification Engineer / Staff Verification Engineer / ASIC Verification / SoC Verification / RTL Verification / Hardware Verification / Semiconductor Verification / Design Verification / SystemVerilog / UVM / Universal Verification Methodology / Constrained-Random Verification / Coverage-Driven Verification / Assertion-Based Verification / SystemVerilog Assertions / SVA / Verification Planning / Verification Closure / Verification Sign-Off / ASIC / SoC / Chipset / Chipset Verification / Die-to-Die / D2D / I/O Verification / High-Speed I/O / High-Speed Interfaces / Networking ASIC / Networking Silicon / UCIe / PCIe / PCIe Gen6 / PCIe Gen7 / Ethernet / Ethernet PCS / Ethernet FEC / SerDes / 224G SerDes / PHY Verification / Protocol Verification / Protocol VIP / Verification IP / VIP Integration / Reference Models / Scoreboards / Testbenches / Verification Environments / Sequences / Agents / Functional Coverage / Code Coverage / Assertion Coverage / Regression Automation / Python / Perl / Scripting / Failure Triage / Debugging / CDC / Clock Domain Crossing / RDC / Reset Domain Crossing / Formal Verification / Formal Model Checking / Connectivity Verification By applying to this role, you understand that we may collect your personal data and process it in line with our privacy policy. Privacy Policy

Ce que vous ferez

Establish and execute verification strategies across blocks, subsystems, and chip-level functions for advanced I/O and chipset solutions. Develop verification plans and maintain reusable SystemVerilog/UVM environments to ensure verification closure and successful tape-out.

Exigences

Requires over 10 years of hands-on ASIC design verification experience with expert-level proficiency in SystemVerilog and UVM. Candidates must have a proven track record of driving verification closure for high-speed interfaces or complex SoCs through tape-out.

Compétences indiquées

• Python · Souhaitée

Autres compétences pertinentes

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• SystemVerilog
• UVM
• ASIC Verification
• High-Speed I/O
• SoC Verification
• Constrained-Random Verification
• Verification Planning
• Verification IP (VIP)
• Reference Models
• Scoreboards
• Assertion-Based Verification
• Functional Coverage
• Die-to-Die Interconnect
• Networking ASICs
• Python
• Perl

Domaines d’emploi

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research