Memory Layout Engineer

🚨 Hiring: Memory Layout Engineer 6+ Years 📍 Location: Ottawa, Ontario, Canada 🏢 Work Mode: Onsite We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced-node technologies and hands-on experience in memory layout development, physical verification, and top-level integration. 🔹 Key Responsibilities • Custom layout development for SRAM, Register Files, ROM & TCAM • Layout optimization for Sense Amplifiers, Control Circuits, I/O Blocks, Bit-Cell Arrays & Decoders • Top-level memory integration within SoC environments • Physical verification and signoff closure • DRC, LVS & Density Checks • IR Drop and Electromigration (EM) analysis and mitigation • Collaborate with Circuit Design, Physical Design & Process teams 🔹 Required Skills • Memory Layout Design • Advanced Node / FinFET technologies • Hands-on experience with TSMC 7nm FinFET • SRAM / ROM / TCAM / Register Files • Physical Verification – DRC, LVS, Density • IR/EM Analysis • Top-Level Memory Integration • Strong debugging and problem-solving skills 🔹 Preferred • Experience with TSMC 6nm / 5nm / 4nm / 3nm • Strong understanding of memory architecture and layout methodologies • Cadence Virtuoso / Calibre experience 🎓 Education: Bachelor’s/Master’s in Electrical/Electronics Engineering or related field. 🚗 Onsite Requirement: Candidates must be able to commute to the Ottawa, Ontario location. 📩 Interested candidates? DM me your updated resume. #Hiring #MemoryLayout #LayoutEngineer #VLSI #Semiconductor #ASIC #SRAM #ROM #TCAM #FinFET #TSMC #7nm #5nm #3nm #DRC #LVS #Calibre #Virtuoso #PhysicalVerification #Ottawa #CanadaJobs

Develop custom layouts for SRAM, ROM, and TCAM while optimizing sense amplifiers and control circuits. Perform physical verification, signoff closure, and top-level memory integration within SoC environments.

Requires over 6 years of experience in memory layout with specific expertise in TSMC 7nm FinFET technologies. A degree in Electrical or Electronics Engineering is required.

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Memory Layout Design
• FinFET Technologies
• TSMC 7nm
• SRAM
• ROM
• TCAM
• Register Files
• Physical Verification
• DRC
• LVS
• IR/EM Analysis
• Top-Level Memory Integration
• Cadence Virtuoso
• Calibre
• Physical Design
• Circuit Design

• Engineering
• Technology
• Manufacturing
• Software

Formation minimale

Baccalauréat

Expérience minimale

5+ ans

Postuler avant le

4 sept. 2026

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Niveau d’expérience

Mid-Senior level

Mode de candidature

La candidature directe est offerte