Design Verification Engineer with UVM, PCIe and UCIe

Must: design verification engineers with UVM, PCIe, UCIe, ethernet verification experience ASIC Programs (Switch/NIC) DV Lead or contribute to verification of 4-5 ASIC design blocks. Develop UVM-based verification environments, sequences, tests, debug, and coverage closure. Strong experience in SystemVerilog/UVM. Experience with PCIe, UCIe 2.0, and Ethernet protocols. Ability to independently own verification deliverables. Support customer collaboration in EST timezone. Required Skills Strong SystemVerilog/UVM verification experience Knowledge and/or hands-on experience with: UCIe 2.0 PCIe Ethernet Ability to own design blocks independently and drive verification closure Responsibilities The DV team is expected to: Own verification of 4-5 design blocks per ASIC Develop and execute sequences Perform test development and debug Drive coverage collection and closure Own end-to-end verification execution for assigned blocks The customer will own the testbench infrastructure.

The engineer will own the verification of 4-5 design blocks per ASIC, including developing UVM-based environments and executing sequences. Responsibilities also include performing test development, debugging, and driving coverage collection and closure.

Candidates must have strong experience in SystemVerilog and UVM, with specific knowledge of PCIe, UCIe 2.0, and Ethernet protocols. The role requires the ability to independently own design blocks and support customer collaboration in the EST timezone.

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• SystemVerilog
• UVM
• PCIe
• UCIe 2.0
• Ethernet
• ASIC Verification
• Design Verification
• Test Development
• Debug
• Coverage Closure
• Sequence Development
• Switch/NIC Verification

• Engineering
• Technology
• Software

Expérience minimale

5+ ans

Langue de l’offre

anglais

Heures de travail

40 heures par semaine

Niveau d’expérience

Mid-Senior level