Design Verification Engineer RTL/ASIC - Remote

Résumé du poste

The Design Verification Engineer will be responsible for verifying digital designs and ensuring that they meet specifications. This includes developing testbench infrastructure and reusable verification components.

Détails du poste

Location: Remote, USA and Canada only Commitment: Full-time preferred; high availability required (40 hours) Duration: Target engagement of ~3+ months RTL Design Engineer Qualifications 3-10 years of experience in digital RTL design Strong proficiency in Verilog / SystemVerilog Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows Ability to write clear design documentation and communicate technical tradeoffs Experience debugging RTL issues using simulation logs and waveform viewers Strong collaboration skills across architecture, verification, and implementation teams Preferred AMBA protocols (AXI, AHB, APB) Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power design Exposure to formal verification or SV/UVM-based design verification Design Verification Engineer Qualifications 3-10 years of experience in design verification Strong proficiency in SystemVerilog and UVM Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols Experience developing reusable verification components and testbench infrastructure Constrained-random verification, functional coverage, assertions (SVA), coverage closure Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression management Familiarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis Ability to write clear verification plans, debug reports, and technical documentation Preferred AMBA protocols (AXI, AHB, APB) Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verification Reusable verification IP, scoreboards, reference models, coverage-driven regression flows

Ce que vous ferez

The Design Verification Engineer will be responsible for verifying digital designs and ensuring that they meet specifications. This includes developing testbench infrastructure and reusable verification components.

Exigences

Candidates should have 3-10 years of experience in design verification with strong proficiency in SystemVerilog and UVM. A solid understanding of digital design fundamentals and experience with EDA tools is also required.

Compétences indiquées

• Verilog · Souhaitée
• Flows · Souhaitée
• Technical Documentation · Souhaitée
• Technical · Souhaitée
• analysis · Souhaitée
• Sens de l’organisation · Souhaitée
• Collaboration · Souhaitée
• Teams · Souhaitée
• management · Souhaitée
• Documentation · Souhaitée
• Development · Souhaitée
• Time · Souhaitée

Autres compétences pertinentes

Relevées dans la description du poste. Confirmez les exigences importantes ci-dessus.

• Verilog
• SystemVerilog
• Digital Design Fundamentals
• ASIC Design Flows
• EDA Tools
• LLM-based Tools
• Debugging
• Collaboration
• UVM
• Reusable Verification Components
• Constrained-random Verification
• Functional Coverage
• Assertions
• Formal Verification
• AMBA Protocols
• Low-power Design

Domaines d’emploi

• Technology
• Engineering
• Software